[Libre-soc-isa] [Bug 1055] update ls004 OPF RFC to include LD-ST-Shifted instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1055

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> missing loads: signed 8bit
> stbus needs to be stbsx

do make corrections directly but do NOT add yet more instructions.

> would be nice to have but icr if part of openpower:
> * both sign/zero extending byte reversed loads
> * byte reversed fp loads/stores

in combination with post-increment this becomes
almost 80 instructions which is alarming.

NO MORE NEW INSTRUCTIONS. please.

byterev GPR was only added for RADIX MMU support which
was punished severely in BE mode.

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