[Libre-soc-isa] [Bug 1053] Separate Vector CRs containing CR8-CR127 from Scalar CR containing CR0-CR7

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1053

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> as i mentioned in the meeting on tuesday, I think we need to specifically
> permit crmove and mcrf between cr0-7 and cr8-127 because the register
> allocator needs to have an inexpensive method of moving cr fields around --
> this can be restricted to svp64 scalar-mode only.

mcrf yes agreed 100%.

> crmove a, b is cror a, b, b

mmmm... it's making me nervous, because that's a really deep-dive into
the decoding.  not only is it "is this a cror" it's "is BFA equal to BFB"
as well as the "is BFA and BFB EXTRA3 marked Scalar" which is already being
proposed here.

with all the other possible aliases (from other crops), which would also have
to be tackled, i'm really not keen. remember this is the *decoder* we're
talking

honestly i feel it would be better to keep that to the crweird mcrfm
instruction, which achieves the same thing and doesn't expect IBM to
"damage" their existing implementation.

https://libre-soc.org/openpower/sv/cr_int_predication/

also mcrfm can handle up to 4 bits at a time.

yes you can't do EQ->LT transfers/copies but you could transfer multiple
bits (either with mcrfm or with mcrf) and then start moving bits in a
single field (anywhere within the 32-bits of the Condition Register)
as a separate instruction.

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