[Libre-soc-isa] [Bug 1045] OPF ISA External RFC ls010 - SVP64 Zero-Overhead Loop Prefix System

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1045

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

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--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> in
> https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;
> h=e06a0faffba0c18150d3ba09c7b16f637885c40f
> 
> you say:
> > It should be self-evident that being able to
> > Vectorise and then truncate a sequence of Atomic Store-Conditional
> > operations at the point where a store was not performed, should
> > be pretty important.
> 
> its importance isn't self-evident to me, because, unless we create an
> extension to lr/sc to have multiple reservations, every store-conditional
> after the first one will always fail,

yep seriously-important catch. we're running out of time and i'm missing
things, so thank you.

> that's all unless you can use vertical-first mode and have it still work or
> something...

yes, it's possible.  LRs will be in sequence with SCs, back round
the explicit-loop to the next register.  DD-FF-conditions spot the
fail and exit the loop.

> If PowerISA gains atomic fetch-add with Rc=1 or similar fetch-op
> instructions, then data-dependent fail-first will actually be useful,
> because the fetch-op instruction wouldn't need a paired load-reserve to
> function.

i'll put a note about leaving the RISC-paradigm concept in, for future
expansion.

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