[Libre-soc-isa] [Bug 1045] OPF ISA External RFC ls010 - SVP64 Zero-Overhead Loop Prefix System

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1045

Jacob Lifshay <programmerjake at gmail.com> changed:

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--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
in
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=e06a0faffba0c18150d3ba09c7b16f637885c40f

you say:
> It should be self-evident that being able to
> Vectorise and then truncate a sequence of Atomic Store-Conditional
> operations at the point where a store was not performed, should
> be pretty important.

its importance isn't self-evident to me, because, unless we create an extension
to lr/sc to have multiple reservations, every store-conditional after the first
one will always fail, because the first one cleared the reservation. this makes
any vectorized store-conditional a misuse of features -- yeah, you can write it
and it runs, but it doesn't usefully do anything different than the scalar
version...

that's all unless you can use vertical-first mode and have it still work or
something...

If PowerISA gains atomic fetch-add with Rc=1 or similar fetch-op instructions,
then data-dependent fail-first will actually be useful, because the fetch-op
instruction wouldn't need a paired load-reserve to function.

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