[Libre-soc-isa] [Bug 937] instructions for bigint shift and prefix-code encode

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Sep 28 20:11:35 BST 2022


--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=10ddc342b1fc075712668bb72463ec811d121949
> for review (feel free to edit/fix), you can see what i attempted
> to do, use a 7-bit shift and if greater than 64 start zeroing out.
> this may not be sophisticated enough and/or conflict with the
> modulo 64 ideas, i leave it with you to best resolve?

it does conflict with the modulo-64 idea.

one benefit of the modulo-64 idea is we don't need a 128-bit rotator, 64-bit
will do afaict -- testing needed:

for the RT <- ((RA || RB) << ((RT) % 64)) >> 64 variant:

n <- (RT)[58:63]
mask[0:63] <- MASK(0, 63 - n)
# mux
v[0:63] <- ((RA) & mask) | ((RB) & ~mask)
RT <- ROTL64(v, n)

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