[Libre-soc-isa] [Bug 905] create Scalar reg access encoding (SVP64-Single)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=905

--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #7)
> (In reply to Luke Kenneth Casson Leighton from comment #6)
> 
> > it would actually be better i feel to propose these ldst-with-pc-relative
> > as new instructions (within the next EXT2nn group) and let them be
> > Vectorised (orthogonally).
> 
> (it already occurred to me to propose LDST-with-shift within the
>  new EXT2nn group to be created under
>  https://libre-soc.org/openpower/sv/rfc/ls001/ )

if you're working on the ldst-with-shift, please reserve 1 setting for
range-checked ld/st with 32/64-bit addresses for webassembly...the range to
check against will be stored in user-visible sprs (details to be specified
later).

e.g. if ld/st shift is:
| prefix PO 0..5 | ext2nn 6..7 | pcrel R 8 | immhi? idk 13..31 |
| suffix PO 0..5 | rt 6..10 | ra 11..15 | rb 16..20 | shift 21..24 | immlo
25..28 | XO 29..31 |

then shift can be (note ld/st shift can access arrays of structs too, so shift
size != ld/st size makes sense):
0 -- rb indexes bytes
1 -- rb indexes half-words (2 bytes)
2 -- rb indexes words (4 bytes)
3 -- rb indexes double words (8 bytes)
4 -- rb indexes quad words (16 bytes)
5 -- rb indexes oct words (32 bytes)
6 -- rb indexes 16-words (64 bytes)
7 -- wasm mode -- rb indexes bytes -- exact process determined by SPRs (TBD)

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