[Libre-soc-isa] [Bug 664] design SVP64 branch instructions (sv.bc)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=664

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
bclr pseudocode:

    if (mode_is_64bit) then M <- 0
    else M <- 32
    if ¬BO[2]  then CTR <- CTR - 1
    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
    cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
    if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
    if LK then LR <-iea CIA + 4

has to become a little more sophisticated:

    lr_ok <- LK
    lsv_ok <- LSVR
    if ctr_ok & cond_ok then
       NIA <-iea LR[0:61] || 0b00
       if SVRMmode.LSV then SVSTATE.next <- LSVR
       if SVRMmode.LRu then lr_ok <- ¬lr_ok
       if SVRMmode.LSVu then lsv_ok <- ¬lsv_ok
    if lr_ok then LR <-iea CIA + 4
    if lsv_ok then LSVR <- SVSTATE

* SVSTATE as well as LR is being captured in LR and LSVR
* SVSTATE as well as LR has the option to be updated if
  the condition test succeeds

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