[Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri May 13 21:53:36 BST 2022


--- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #40)

> that isn't what you want...you want the existing maddld instruction, but
> extended to have rt and rc be 128-bit register pairs.

damn.  which is 4-in, 2-out.  6 64-bit register hazards is far too much.

> another alternative for fp dot product with higher precision is just doing a
> vector fmul followed by a tree reduction fadd, which retains most of the
> precision due to values being rounded O(log N) times rather than O(N) times
> from a serial reduction.

like it.

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