[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #27 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #26)
> added python generator for tree-reduce with remap (passed in as a dict or
> something else indexable)
> 
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=2fe0ce6285864927127d8226171c566886b87e89

I got thoroughly distracted trying to make pretty ascii-art tree graphs for use
by the above generator, WIP code here:
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=f684acfa32ba1ef8c52abc5876da2b73696862dd

(lkcl, please don't remove all the type annotations or refactor all the code in
text_tree_graph.py, it makes it waay easier for me to figure out, i'll remove
them when I'm done...unless you want to finish getting it working? we should
probably put this off for several months at least...)

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