[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remapyield.py;hb=HEAD

the function there, is the earliest REMAP algorithm first
implemented, done as a generator.  used in ISACaller directly
which is a bundle of fun because ISACaller itself uses yield.

there is also an actual matrix mult demo/test somewhere.

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