[Libre-soc-isa] [Bug 862] setvl Vertical-First mode issues with predicates, extend setvl to 64 bit

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=862

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|setvl Vertical-First mode   |setvl Vertical-First mode
                   |issues with predicates      |issues with predicates,
                   |                            |extend setvl to 64 bit

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=6cac17aa4a16c30c337a26cb083138d5fbc0ef74

here was an idea of having a CTR reading mode.  VF mode needs some bits
to say which preficates are to be protected (made read-only).  therefore
swap vf with ct bit, and move vf mode to 24 bit RM.

then, add bits 4 for r3 r10 r30 CRf
then, allow CR Predicate to be selected starting
from CR16,CR32,CR48,CR64 (2 bits)

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