[Libre-soc-isa] [Bug 553] svp64 register mapping to accomidate AltiVec vectors expanding fp registers

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Jun 12 22:21:04 BST 2022


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
             Status|DEFERRED                    |RESOLVED
         Resolution|---                         |INVALID

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #7)

> I've proposed the high halves of f0-63 be f64-127.

i know.  it's not happening.  and it is completely unnecessary.
when someone puts SVP64 on top of Scalar VSX, it happens automatically
and implicitly because the VSX registers already have the mapping
that you describe.

please leave this bugreport as closed and invalid.

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