[Libre-soc-isa] [Bug 553] svp64 register mapping to accomidate AltiVec vectors expanding fp registers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=553

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |DEFERRED
         Resolution|INVALID                     |---

--- Comment #8 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #7)
> it's still valid, because those quad-precision instructions are already
> defined to use vsx registers. we will still want some kind of mapping
> because we want the scalar 128-bit instructions to use the exact same
> registers as are used for 128-bit vector elements.

marking as valid.

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