[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)

> no, it's just integer predicates that are bit-reversed. CR predicates are
> already logically laid out as a vector of bits rather than an integer, so
> they are already in vector element order and don't need reversing.

the fields are nibbles (4 bit) and if there is to be numbering reversal then
it should be consistently applied, even to nibbles.

that it is quite insane to consider should give a clue that reversal of integer
predicates is equally as insane.

i repeat: if we had totally separate predicate mask regfiles this would not be
an issue, i would be agreeing with you 100%, that the predicates could and
should respect the current MSB ordering.

it is the fact that the regfile is MMX-esque (8/16/32/64 within a 64 bit GPR)
that makes the idea of doing anything other than strictly treating the regfile
as byte-addressable LE-ordered SRAM completely insane.

i am not kidding when i say that it would take many months to do a full audit
of the implications of this idea.

it is simply too much.

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