[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #13 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
the problem is if we don't use the already existing vector support in LLVM, it
makes our problem more than 10x larger, from just needing to add SVP64 to the
powerpc target which is relatively simple (probably less than 30kloc) into
needing to rewrite/duplicate major portions of LLVM and Clang and Rustc and
Flang and all other language frontends (probably 100k to millions of loc) cuz
we'd need to rewrite/duplicate everything everywhere that touches vectors:
optimizations, frontends, backends, etc.

imho that approach is patently absurd unless you are able to spend >$100M on
dozens of programmers over several years.

also, programmers everywhere will hate us if we don't map the pre-existing llvm
vectors to svp64 instructions because then they'll have to rewrite their code
if they want it to go fast on svp64 -- they'll probably mostly ignore svp64 and
we will have mostly failed in our mission to make cpu vectors easier to work
with.
> 
> and if SVP64 is damaged by fitting with how SIMD and
> other Vector ISAs have been done (with their explicit intrinsics),
> that job will be made far harder.
> 
> remember: if we follow how things are done for other Vector ISAs
> in LLVM, we have ONE AND A HALF MMMILLLLION vector intrinsics.

not actually, llvm intrinsics can have constant and/or metadata arguments,
allowing you to share one intrinsic between many different operations.

Also, when first starting out, imho we should add the functionality to llvm
that is basically what RISC-V V implements (mapping llvm's
architecture-independent fixed/scalable length vector operations to SVP64
instructions, allowing us to reuse the 10s of millions of lines of code spread
across the ecosystem that targets architecture-independent fixed-length and/or
scalable vectors, and mostly leave the rest for later).

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