[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
LLVM currently assumes that vectors (like SIMD) of bits are laid out such that
bit ordering always matches byte ordering (it doesn't have a concept of
different bit ordering vs endian) -- BE starts from the MSB as the first vector
element, going to the LSB as the last vector element -- LE starts from the LSB
as the first vector element through to the MSB as the last vector element.

I found that in LLVM's code for converting between bitvectors and their memory
layout (implementation of bitcasting for vector constants, to be specific).
that was a while ago and i was just now reminded again, so I don't have a link
to LLVM's code right now (too tired to look at the moment).

Because that assumption is baked into LLVM, probably spread throughout the
code, making it quite difficult to split out bit order as independent from byte
order, we will probably want to take the path of least resistance and change
SVP64 to have bitmasks be MSB0 in BE, and LSB0 in LE.

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