[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)

> it works by having an array of indices which initially start off 0..VL
> and whenever you would like to *have had* a mv, instead of performing
> an actual mv, the data is left *in place* but the "redirect" array adjusted
> dynamically such that a subsequent ADD will take the data from the
> in-place location

this btw was exactly how i worked out the in-place DCT algorithm
(which is a world-first achievement, to have in-place DCT i.e.
without having to use double the number of vector registers)

in that case it turned out that the algorithm used for the index
remapping was incredibly simple and elegant (idx XOR (idx>>1))

but to get to that stage took a lot of incremental steps (6 weeks worth)
and one of those steps is to rewrite the algorithm as a "yield"er


i have a sneaking suspicion that even in the case where there is only one
ADD needed because all but 2 elements are predicated out, the remapping
will still work because the remapping will identify (eventually) the
rightmost element.

the only case i think not covered would be when *all* elements except
*one* are predicated out.  this would be expected to perform a straight
MV, copying the element into element 0 and that will not happen.
it can be "fixed" by adding one extra element (a zero)

one unit test that will definitely be needed and quite interesting
is when the predicated elements are all in the top half (covered by
"other").

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