[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
followup: now i think about it, index-redirection will be needed
on *both* i *and* other, such that


     reg[redirect1[i]] += reg[redirect2[other]]

and then, obviously, the yield on RT to return redirect1[i] NOT i,
and the yield on RA to return redirect2[other] NOT other

the first stage of the remaps will therefore compute the tables
redirect1 and redirect2 such that the MV operation is entirely
redundant.

one critically important reason for this is Vertical-First Mode

[yes parallel reduce will work in Vertical-First Mode!!!]


if there is a MV operation substitution then any given ADD (or
whatever) will SILENTLY be replaced with a MV and the programmer
will have absolutely no idea why.

yes, really, parallel-reduce in VF mode i can already see some useful
things there, involving multiple operations tracking the exact same
reduction schedule: doing a divide on the src operand or computing
the inputs to the schedule on-the-fly, or even (this would be horrific)
exiting the reduction loop early depending on partial results,
or "fixing" the values if they happen to overflow.

lots of possibilities and they are all actively interfered with if a
MV is involved

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