[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
def reduce(vl, vec, pred):
    step = 1;
    while step < vl
        step *= 2;
        for i in (0..vl).step_by(step)
            other = i + step / 2;
            other_pred = other < vl && pred[other];
            if pred[i] && other_pred
                vec[i] += vec[other];
            else if other_pred
                vec[i] = vec[other];
            pred[i] |= other_pred;


transform ==>

def reduce(vl, vec, pred):
    step = 1;
    indices =[]
    while step < vl
        step *= 2;
        for i in (0..vl).step_by(step)
            other = i + step / 2;
            other_pred = other < vl && pred[other];
            if pred[i] && other_pred
                indices[something] = other
            else if other_pred
                indices[something] = other
            pred[i] |= other_pred;

    step = 1;
    while step < vl
        step *= 2;
        for i in (0..vl).step_by(step)
            other = i + step / 2;
            vec[i] += vec[indices[somethingother]];

and that to then be further morphed to a REMAP yield form

-- 
You are receiving this mail because:
You are on the CC list for the bug.