[Libre-soc-isa] [Bug 794] SVP64 REMAP for utf8

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=794

--- Comment #37 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #36)
> I got UTF-8 validation to work!

frickin-A!

> I had to do a bunch of instruction substitution to work around
> limitations/bugs in the instruction simulator, most of the limitations/bugs
> are documented in the comments on the function that generates the assembly:

see comment #35 

and you can use "svstep." instead of this:

 190         f"sv.addi *{cur_bytes + 1}, *{cur_bytes}, 1",  # create indexes

and this:

 183         # clear cur bytes, so bytes beyond end end up being zeros
 184         f"setvl 0, 0, {vec_sz}, 0, 1, 1",  # set VL to vec_sz

is what data-dependent fail-first is for (although it needs implementing)
it will auto-truncate VL at the terminating zero.  you need to set the
"/vli" option to include the failing-terminating-zero.

> 
> I also implemented a better memory dump for logging, like hexdump -C:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commit;
> h=661ae80360644dfe3a9e7f3610d534cc3a7e545f

brilliant

> I also implemented support for svp64 prefixed instructions that have a
> libre-soc-custom suffix, e.g. sv.maxu:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commit;
> h=0e80cab3b809d432354ca05464e95dc53db11b64

mmm... this may have damaged detection of "sv.fmadds."
please check that.

+        if not v30b_op.endswith('.'):
+            v30b_op += rc
         # argh, sv.fmadds etc. need to be done manually
         if v30b_op == 'ffmadds':

> I also added support to Expected for when tests don't care what so, ov, and
> ca get set to, those can just be set to None:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commit;
> h=07f5f22461d5eda844141b2ffd33e021d2b43ffb

excellent.

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