[Libre-soc-isa] [Bug 794] SVP64 REMAP for utf8

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=794

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
  44         else if _RA != 0         then
  45             if (RA) >u 0b1111111 then VL <- 0b1111111
  46             else VL <- (RA)[57:63]

i have no idea why when i added exactly this a few days ago
it is not already committed, duh

+        if Rc = 1 then
+            if step = 0 then c <- 0b001
+            else c <- 0b010
+            CR[32:35] <- c || XER[SO]

this should already be done and does not look correct
according to spec

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/caller.py;h=f3d9d8085115bc0c053116707b37a2cba5e40d6b;hb=HEAD#l1665

ah hang on yes check_step_increment is not called on 32bit
scalar ops. that may need fixing esp. for "svstep."

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