[Libre-soc-isa] [Bug 794] SVP64 REMAP for utf8

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Aug 26 10:08:52 BST 2022


https://bugs.libre-soc.org/show_bug.cgi?id=794

--- Comment #33 from Jacob Lifshay <programmerjake at gmail.com> ---
As an example of log filtering:
> SILENCELOG='!instr_in_outs' python src/openpower/decoder/isa/test_caller_svp64_utf_8_validation.py

outputs:
<LogKind.Default: 'default'> silenced
<LogKind.InstrInOuts: 'instr_in_outs'> active
<LogKind.SkipCase: 'skip_case'> silenced
running test:  case_empty {'data': b'', 'expected': 1}
<snip>
0x003C: 58A40FB7 .long 0x58A40FB7 # setvl. 5, 4, 8, 0, 1, 1
read reg r4: 0x0
write reg CR: 0x20000000
write reg SVSTATE: 0x1000000000000000
write reg CTR: 0x0

0x0040: 418200BC bc 12, 2, final_check # beq final_check
write reg CTR: 0x0
write reg CR: 0x20000000
write reg LR: 0x10000000

0x00FC: 580001B6 .long 0x580001B6 # setvl 0, 0, 1, 0, 1, 1
read reg r0: 0x15CEE3293AA9BFBE
write reg CR: 0x20000000
write reg SVSTATE: 0x204000000000000
write reg CTR: 0x0

0x0100: 05400100 .long 0x05400100 # sv.cmpli 0, 1, 45, 240
read reg r45: 0x0
write reg CR: 0x80000000

0x0108: 4080FFEC bc 4, 0, fail # bge fail
write reg CTR: 0x0
write reg CR: 0x80000000
write reg LR: 0x10000000
<snip>

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