[Libre-soc-isa] [Bug 794] SVP64 REMAP for utf8

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Aug 24 06:19:15 BST 2022


https://bugs.libre-soc.org/show_bug.cgi?id=794

--- Comment #23 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #22)
> (In reply to Jacob Lifshay from comment #21)
> > thinking about it, it would be very useful to have a quick way to do what
> > risc-v v's vslideup/vslidedown do:
> > https://github.com/riscv/riscv-v-spec/blob/
> > b6368b3c44d775f8eb01c7ce0ad017db19944aa7/v-spec.adoc#163-vector-slide-
> > instructions
> 
> if register aligned a simple sv.ori rt, rt+1, 0 does
> that. /mrr inverts the loop order.
> 
> except if nonaligned then REMAP offset is needed.
> 
> > it can be done using remap, but takes several instructions to be set up.
> 
> two. that's hardly "several", is it.

you forgot the setvl again since svshape put junk in it...

I didn't see how to get the svshape instruction to set offset...

Also, the algorithm constantly needs to switch between several offsets, making
a dedicated mode desirable.

-- 
You are receiving this mail because:
You are on the CC list for the bug.


More information about the Libre-SOC-ISA mailing list