[Libre-soc-isa] [Bug 794] SVP64 REMAP for utf8

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=794

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #21)
> thinking about it, it would be very useful to have a quick way to do what
> risc-v v's vslideup/vslidedown do:
> https://github.com/riscv/riscv-v-spec/blob/
> b6368b3c44d775f8eb01c7ce0ad017db19944aa7/v-spec.adoc#163-vector-slide-
> instructions

if register aligned a simple sv.ori rt, rt+1, 0 does
that. /mrr inverts the loop order.

except if nonaligned then REMAP offset is needed.

> it can be done using remap, but takes several instructions to be set up.

two. that's hardly "several", is it.  and if in a loop
and there are no other uses, the svshape can be set once,
outside, and the svremap on-demand as needed. leave SVSHAPE0-3
alone, activate them when needed, not setting the "persist"
bit. then the remaps apply to the next instruction only
and switch off again... *without* changing SVSHAPE0-3 though.

> imho we should use one of the svshape reserved combinations for this. it
> should not set vl and mvl as part of svshape.

the 3 current purposes for svshape at the moment are to
absolutely minimise those 3 uses: matrix dct fft. anything
else is a welcome bonus.

> the example code I've been writing works around that by expanding each byte
> to fill a whole 64-bit register -- pretty wasteful.

First approximation, good enough, then work out what can
be done better.

for example by doing 64-bit svshape (sv.svshape) an extra
24 bits magically becomes available. i have no problem
at all in some of those bits expanding the options that
had to be limited or missed entirely for the 32 bit svshape,
such as the offset.

matrix mode is perfectly capable of being set to 1D which
when combined with offset gives the desired result here.
5+1 bits are also enough to set a small range of remap
options as well (see svindex for how that can be done)

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