[Libre-soc-isa] [Bug 817] Big Integer Math (sv.adde, sv.subfe, sv.madded, 128 by 64-bit -> 64-bit div/rem, maybe more...)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Apr 26 18:14:15 BST 2022


--- Comment #35 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #34)
> https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;
> h=b6044fdb84bea61887999ffa5e17543fa91b8f89
> good, whew.  i have to explain all this :)
> caveat here: divmid2du communicating "overflow", that's... expensive.
> CR0 and/or OE=1.  OE=1 is not going to fit into VA-Form EXT04.
> each is an extra register.

we'd want writing to CR0, since it saves an instruction...otherwise you'd need
the move OV to CR0 instruction before the conditional branch.
> making the operation always "divmid2du." would do the job, but, dang,
> that's 3-in, 3-out.

well...is 3-in 3-out more expensive than needing an extra compare instruction
in an important use of divmodqdu?

i guess we could, instead of writing CR0 or OV, just have it compare like so:
cmpl n_hi, d
divmodqdu qhat, d, n_lo, n_hi

the cmpl takes extra resources...in a non-superscalar system takes an extra
clock cycle. we can't put it after the divmodqdu (which would save a clock
cycle on non-superscalar systems) since n_hi is overwritten, though otoh we
likely need to have another copy of n_hi in a register anyway and cmpl could
just use that.

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