[Libre-soc-isa] [Bug 686] create Power ISA test API

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=686

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok, right, so are you thinking along the lines of (similar to how
nmigen Record works, and also PowerDecoder RowSubset):

* a list of regnames
* a base class (inherited by both HDLState and SimState)
* a function in the base class which takes the regnames and
  uses getattr to access the "reg to be compared"

something like that?

do bear in mind a couple of things:

1) the existence of some regs (e.g. Floating Point) is conditional.
   both the HDL and simulator this is optional

2) the *number* of regs can vary.  Power ISA v3.0B has only 32 GPRs
   and 32 FPRs, but SVP64 has 128 for both *and* will have *16*
   32-bit CRs.

3) SPRs (which you can pick up a full list *already* from
   the power_enums.py class are so numerous we had to dynamically
   allow only a subset of them, as determined at runtime.

so you have to bear in mind, the total numbers and size may vary,
in the final version, and so has to be adaptive.

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