[Libre-soc-isa] [Bug 686] create Power ISA test API
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Fri Sep 10 16:29:43 BST 2021
https://bugs.libre-soc.org/show_bug.cgi?id=686
--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #25)
> https://git.libre-soc.org/?p=soc.git;a=commit;
> h=79e28bfdc43c60de661599a02726af245aaa74d3
>
> blocked comments to be removed.
great. i'll run it shortly.
ok the pep8 whitespace mods, i have difficulty discerning
them from functional-related changes. do keep to "one purpose, one
commit" (see HDL_workflow).
i read this in the diff, and wondered, "what functional change
is it making? ah it's just whitespace"
def setup_regs(pdecode2, core, test):
@@ -71,7 +72,7 @@ def setup_regs(pdecode2, core, test):
print("setup cr reg", hex(cr))
for i in range(8):
#j = 7-i
- cri = (cr >> (i*4)) & 0xf
+ cri = (cr >> (i * 4)) & 0xf
#cri = int('{:04b}'.format(cri)[::-1], 2)
print("setup cr reg", hex(cri), i,
crregs.regs[i].reg.shape())
@@ -121,7 +122,7 @@ def setup_regs(pdecode2, core, test):
if sprname == x.name:
print("setting slow SPR %d (%s) to %x" %
(i, sprname, val))
- if not sprname in mmu_sprs:
+ if sprname not in mmu_sprs:
yield sregs.memory._array[i].eq(val)
else:
yield from set_mmu_spr(sprname, i, val, core)
@@ -148,6 +149,7 @@ def setup_regs(pdecode2, core, test):
> One thing I think would be beneficial is adding in a static class with
> register names. Given everything from the state class can be accessed as a
> list, enumerating with register name lists would allow just one generic
> compare function for every type of register while being descriptive. Would
> only need to add an additional argument to compare function.
mmm, yeah, that'd work. openpower/consts.py would be a good place
to include them: do (as a separate single commit) put explanatory
comments, openpower-isa is a reference as much as anything.
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