[Libre-soc-isa] [Bug 686] create Power ISA test API
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Tue Sep 7 14:26:41 BST 2021
https://bugs.libre-soc.org/show_bug.cgi?id=686
--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
kyle, so that this is clear to you, can you first take a look at test_core.py
check_regs() and split it into THREE functions:
1) a function that extracts registers from the HDL core
2) a function that extracts registers from the sim object
3) a function that compares the two.
example:
147 def check_regs(dut, sim, core, test, code):
148 # int regs
149 intregs = []
150 for i in range(32):
151 if core.regs.int.unary:
152 rval = yield core.regs.int.regs[i].reg
153 else:
154 rval = yield core.regs.int.memory._array[i]
155 intregs.append(rval)
156 print("int regs", list(map(hex, intregs)))
157 for i in range(32):
158 simregval = sim.gpr[i].asint()
159 dut.assertEqual(simregval, intregs[i],
160 "int reg %d not equal %s. got %x expected %x" % \
161 (i, repr(code), simregval, intregs[i]))
becomes:
147 def get_core_hdl_regs(dut, sim, core, test, code):
148 # int regs
149 intregs = []
150 for i in range(32):
151 if core.regs.int.unary:
152 rval = yield core.regs.int.regs[i].reg
153 else:
154 rval = yield core.regs.int.memory._array[i]
155 intregs.append(rval)
... return intregs
and:
... def get_sim_regs()
157 for i in range(32):
158 simregval = sim.gpr[i].asint()
... simregs.append(...)
... return simregs
and:
def check_regs()
get_sim_regs()
get_core_regs()
for i, (regsim, regcore) in enumerate(zip
(simtegs, coreregs):
dut.assertEqual(etc etc)
it should be pretty obvious where that leads: a class is needed which
"collects" GPRs, CRs, etc etc etc etc. rather than lists, a class *containing*
lists.
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