[Libre-soc-isa] [Bug 615] talk to binutils and gcc developers about acceptable sv assembly format

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=615

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #7)

> if the dot in register numbers is the only problem, we might as well drop
> it.  v and s will do just fine ending the register number.  but I'm curious
> as to what motivated segher's objections.  was it because '.' could be part
> of a number?

yes, he pointed out that "." anywhere will not be well received.
i suspect the only reason that "." is allowed at all is because
it's part of the OpenPOWER v3.0B spec for mnemonics:

   add.   => set Rc=1
   add    => set Rc=0


he did say we need some way to support numerical-only register numbers.
to achieve that i am inclined there to say "screw it" and simply have:

   svadd/extra=0xNN  N1, N2, N3

as an "option" where the N1, N2, N3 is *verbatim* v3.0B *not* the
*SV-augmented* register numbers

i.e. 

   svadd/extra=0xNN  N1, N2, N3

would translate to:

   .long 0x...NN    # that NN is the same bits from extra above
   add  N1, N2, N3  # these do not change

in other words the actual v3.0B augmented opcode is clearly unmodified

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