[Libre-soc-isa] [Bug 650] write rfc for OpenPower fpr <-> gpr moves/conversions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=650

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
|  0-5   | 6-10 | 11-15  | 16-25 | 26-30 | 31 |
|--------|------|--------|-------|-------|----|
|  Major | RT   | //Mode | FRA   | XO    | Rc |
|  Major | FRT  | //Mode | RA    | XO    | Rc |

ha, that looks allright for FPint cvt.  meshes with the existing
format, with the Mode field fitting into RB.

unfortunately, i bet you that no illegal instruction exception is
raised in the existing fcfids (etc) which means we can't fit into
the existing XO with bits 11-15 being all zero.

if that's the case an entirely new XO set will be needed.
i'd strongly suggest reserved encodings for all 5 bits
11-15 throw an illegal instruction exception. this allows
software emulation of future Mode variants if there are any.

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