[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #114 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #113)
> (In reply to Jacob Lifshay from comment #112)
> > (In reply to Luke Kenneth Casson Leighton from comment #111)
> > > https://libre-soc.org/openpower/sv/svp64/appendix/
> > > 
> > > it just occurred to me that we actually need two different kinds of
> > > reduction:
> > > 
> > > * scalar accumulator O(VL)
> > 
> > assuming you mean serial reduction, where none of the per-element operations
> > can be run in parallel (except for a few special cases).
> 
> ah good point.  MIN/MAX, XOR, OR, AND are definitely paralleliseable (into
> an accumulator), probably MUL and ADD as well.

yup, for integer ops only (though fp max and min would also work, depending on
the exact IEEE754 function used). anything that is an associative operator.

>  things like SUB, DIV, those
> are a little weird.

And the majority of floating-point ops.

though integer sub could be parallelized by doing negations and a parallel
add-reduce.

> > > * vector tree-based map-reduce O(VL log VL)
> > 
> > parallel reduction
> 
> yep nice point, noted.

it just occurred to me that when context-switching in the middle of a
parallel-reduction, the vstart register is not actually the starting index, so
we should call it resume-step (the step at which the next SV instruction
resumes its progress) or something.

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