[Libre-soc-isa] [Bug 553] svp64 register mapping to accomidate AltiVec vectors expanding fp registers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=553

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
apologies, jacob, the information i am holding in my head (unimplemented) is
becoming beyond my capacity to explain.  coupled with the difference between
electrical and chemical neural recall (chemical is long-term and often
difficult to access) i am basically getting symptoms best known by the
phenomenon "writer's block".

in essence i "know" something is "not right" but am literally unable to say why
because my memory recall is not responding immediately, and due to the length
of time that has gone by on some of the details (2 years) it may actually be
*several days* before details emerge sufficiently to be able to *begin* to
describe them to you.

bottom line is that when you push and push and push basically demanding an
exact and precise response *i cannot give you one* and this is terribly
frustrating for me, not to be able to speak and give you the "exact" answer
that you expect.

the only way that this is going to work is if implementation proceeds *right
now*, without further delay, getting the core details out into code that can be
reviewed, understood, and incrementally adjusted accordingly.

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