[Libre-soc-isa] [Bug 572] elwidth and indirection: two vectors, one width

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=572

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #1)
> I've just realized that the phrase "two vectors" in the subject may be both
> inaccurate and misleading.
> 
> so, to try to be abundantly clear, I'm mainly talking about the (potential)
> vector of addresses, and the (potential) vector of objects it/they refer to,
> NOT about the vector register that will hold the loaded values.

you are therefore probably talking about indexed mode.

i removed indexed mode when illustrating the pseudocode for you because you
asked about what is termed "unit stride" mode.

> also, I am mostly sure that in the end only one of the (potential) vectors
> ends up being an actual vector, though subvl>1 might actually turn out to
> make both of them actual vectors.

remember SUBVL is effectively simply a multiplier (num actual elements
VL*SUBVL) and that SV is never actually switched off: scalars are just "when
SUBVL=1 and VL=1" 

> it also occurs to me now to wonder now whether there is a any case (or way
> to express) that both are scalars, as in, load this single value from
> memory, and then place it in all elements of the destination vector.

yyyepp.  that's standard twin predication VSPLAT behaviour on top of a LDST
"thing".

although i think i see where you're going with this: i will have to check.

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