[Libre-soc-isa] [Bug 571] svp64 vector loads: sub-dword selection before or after byte-reversal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=571

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #5)
> the pseudocode in comment 2 (and in bug 567's comment 2; I'd somehow missed
> the email about it, and went straight to the simple_v specs as if that was
> the only answer) makes this mostly clear, thanks
> 
> the only unstated implication that comes to mind is that mem and bytereverse
> are supposed to be polymorphic themselves,

mm.... strictly... let me think it through.... this was never true.  the
lb/lh/lw/ld even on the older RISC-V version of SV (ok ok the RV version didn't
*have* bytereversal) had to take the width from the operation, not the SV
polymorphic/elwidth overrides.

with the mem-load (and now with OpenPOWER the bytereversal) being a property of
the memory not the core it was - and still is - on the "other side".

most operations in OpenPOWER simply don't allow specifying a width: LD/ST is
one of the very few.


> and operate on integer types of
> the source-vector element width.
> 
> this can be guessed, but it's not certain from the notation; I think adding
> the bit-width as a parameter to both pseudofunctions would make it
> crystal-clear.

hmm if all of the SV context parameters are added it makes the line too long.
what i will do instead is add "svctx" as a parameter, then people
can go "svctx.elwidth, oh ok that's passed in"

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