[Libre-soc-isa] [Bug 571] svp64 vector loads: sub-dword selection before or after byte-reversal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=571

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > the only possible interpretation of the question which might make sense is
> > illustrated by the ARM NEON LDR (Load-Reverse) instruction, where they
> > perform *total* byte-reversal, bytes 0-15 in memory get placed into register
> > bytes 15-0
> 
> Sorry, that's just incorrect: the LDR instruction is ARM's standard
> load-register instruction.

ah, interesting, thank you for the correction.  it was used in that NEON-LLVM
write-up.  my take on LDR (on NEON regs) from what i could infer it
"effectively" performed byte-reversal [in BE mode], i assumed that was its sole
purpose.

i need to add a section on the Appendix covering this, the new one:
https://libre-soc.org/openpower/sv/svp64/appendix/

not the old one:
https://libre-soc.org/simple_v_extension/appendix/

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