[Libre-soc-isa] [Bug 571] svp64 vector loads: sub-dword selection before or after byte-reversal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=571

Jacob Lifshay <programmerjake at gmail.com> changed:

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--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> the only possible interpretation of the question which might make sense is
> illustrated by the ARM NEON LDR (Load-Reverse) instruction, where they
> perform *total* byte-reversal, bytes 0-15 in memory get placed into register
> bytes 15-0

Sorry, that's just incorrect: the LDR instruction is ARM's standard
load-register instruction. In LE mode, the bytes are not reversed, in BE mode
they are, but only because all memory accesses use reversed endian by default,
not because LDR is special.

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