[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
interesting anomaly, good catch.

ok so integer predication is defined as scalar only. i.e. only ONE integer
register is utilised, 64 bits in length, NOT a vector of integers.

this meshes well with, or more specifically *is* the reason why VL is
restricted to 64.

we are NOT repeat NOT going to change the definition of scalar integers, so the
behaviour is DEFINED as how v3.0B integers are defined.

if a user were to load an integer into a register then the lowest arithmetic
bit (numbered 63 by IBM using their MSB0 convention, sigh) would be that bit
used as the first predicate bit.

i say "lowest arithmetic bit" to mean, according to v3.0B standard scalar
behaviour, "the bit which, if the same register were to have the constant 1
placed into it with addi rN, r0, 1 this would result in the MSB0-numbered bit
63 containing a 1 and all other bits would be zero"

if a user used the wrong ld operation (ld rather than ldbrx) then that is their
lookout: i.e. it is an error on their part.

this also affects (or, doesn't) the new cr-to-int transfer routines that have
to be added to help with predication in general.  these should be modelled
after how mtcr and mfcr work in the scalar v3.0B spec.

i will go through the relevant pages and make sure there are sections on this.

https://libre-soc.org/openpower/sv/cr_int_predication/

-- 
You are receiving this mail because:
You are on the CC list for the bug.