[Libre-soc-isa] [Bug 569] New: svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

            Bug ID: 569
           Summary: svp64 register predicates vs BE arrays of bits
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Other
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: oliva at libre-soc.org
                CC: libre-soc-isa at lists.libre-soc.org
            Blocks: 213
   NLnet milestone: ---

Bit arrays (that don't exist in C, but that exist in other languages) and bit
fields are allocated from most significant to least significant bit, in big
endian mode, which is the opposite order of little endian.

Even with implicit byte-reversal on load, this won't bit-reverse, which  would
be required for predicates to be represented in such a natural way in BE.

We probably have to document this constrain on BE, and state that programmers
must arrange for bits to land in the predicate register so that the LSBit (2^0)
holds the predicate for vector element 0, and so on.

This can be as simple as encoding the value to be loaded into the predicate
register as an integral type, computed by ORing the bits, each one shifted left
by the index of the vector element they apply to.  Holding an integer value
computed this way in memory, in the cpu-configured endianness, whatever its
width, and loading it into the predicate register with that width, will yield
the intended predication.

Bit arrays indexed by vector element width, or 1-bit-fields declared in the
same order as vector elements, will only correspond to the intended vector
elements if the CPU is in LE mode.

In BE mode, it does NOT help to configure the specific predicate type as being
in LE mode.  In order to be usable for predication, it needs a mixed-endianness
representation, with bytes laid out as big-endian, because of byte-reversal on
load, but with bits laid out as in little-endian, because of the absence of
bit-reversal.


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=213
[Bug 213] SimpleV Standard writeup needed
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