[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #75 from Alexandre Oliva <oliva at libre-soc.org> ---
I thought I'd already shown that I understand how ld and ldbrx work.  What else
remains so we can finish this exchange and get to my suggestion, that is not
related with this?

> a dynamic LE-BE regfile

My suggestion of iteration order in sub-register vector elements is unrelated
to this.

Should I file a separate bug for it so that you'll read it?

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