[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #74 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #72)
> > it's not going in
> 
> please spell out what it is that's not going in.

the topic of this thread (a dynamic LE-BE regfile)  the bugreport is to be
closed as either INVALID or WONTFIX.

the decision, which is categorically final, is that the regfiles remain LE
ordered meaning, just as is done in ARM NEON and Intel MMX.

the words "it's not going in" refer to Jacob's ideas of adding a full 8x8
bytelevel crossbar in front of every 64 bit regfile port in order to perform
simultaneous multiple element byteswapping up to the SIMD ALU width of 64 bit.

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