[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #70 from Alexandre Oliva <oliva at libre-soc.org> ---
I'm not at all concerned with muxes, my suggestion has nothing to do with them,
but I am familiar with hardware gates and muxes and that sort of stuff, thank
you very much.

my suggestion is about iteration order only.  since in a vector you'll normally
iterate over all elements, you need the gates to select each of the sub-units. 
the only thing that changes is which sub-units you visit first.

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