[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #55 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #53)
> (In reply to Alexandre Oliva from comment #50)
> > do you see now why it doesn't make sense that the conversion from BE to LE
> > (or vice versa) places the MSByte in the LSByte?
> 
> deep breath: it doesn't matter if it "makes sense", it's what the actual
> code - the simulator, the HDL of microwatt and the HDL of Libre-SOC -
> actually do.

Yes, and Alexandre and I are saying that the CPU should be changed for the
software reasons explained previously:

registers should keep their contents conceptually in the data endian mode the
cpu is currently in, all arithmetic operations should byteswap from the
registers' endian mode to LE (or whatever endian the ALU is implemented in) for
operations byteswapping at the element-size for the operation, then back to the
data endian mode to store the results in registers.

In BE mode, all of those byteswaps swap between BE in the registers and LE for
the ALUs.

In LE mode, all of those byteswaps swap between LE in the registers and LE for
the ALUs -- here the byteswaps are actually no-ops.

Switching between BE and LE mode by flipping the mode bit in the appropriate
SPR will byteswap all registers at 64-bit width in order to keep their values
for OpenPower v3.x compatibility.

All the above is how it looks to the ISA-level programmer. The hardware can and
should implement it differently but it has to end up looking like the above.

Possible implementation: Byte-swapping networks are added to ALUs that can swap
at all sizes the ALUs support (so a 16-bit op tells the byte-swapper to swap or
not at 16-bit size, a 32-bit op tells the byte-swapper to swap or not at 32-bit
size, and so on for other sizes), the data busses and argument/result latches
store results in the CPUs current endian mode.
the registers are always stored in LE mode for 64-bit values, the register R/W
ports byteswap at 64-bit size if the data-endian mode SPR bit is BE, otherwise
are passthroughs.

changing the data endian mode SPR bit causes a total pipeline flush, flips the
bit (enabling/disabling the 64-bit byteswapper at the registers), then resumes
the CPU.

the PC and SPR registers are always kept in LE form, since they are not
byte-addressable, making the CPU simpler. instructions that copy ISA-level
register values from/to SPRs (or PC) will byteswap at the appropriate size as
part of getting the actual value of the register from the internal
busses/latches.

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