[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #54 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
alexandre i have another way to help you think this through.  what behaviour do
you expect - in the scalar implementation - of the HDL to perform when
transferring data from memory into the register file:

* ld     LE: ordering of the MEANING in regfile is in {insert order}
* ldbrx  LE: ordering of the MEANING in regfile is in {insert order}
* ld     BE: ordering of the MEANING in regfile is in {insert order}
* ldbrx  BE: ordering of the MEANING in regfile is in {insert order}

following on from that, what behaviour do you expect in the ALUs in each case?
specifically: how should the ALUs read and write the data to and from the
regfile?

there should be (potentially) two orders at that point (two "meanings" as you
term them).

* following {insert order above} into regfile, ALUs read/write in {insert
order}
* following {insert order above} into regfile, ALUs read/write in {insert
order}

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