[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #52 from Cesar Strauss <cestrauss at gmail.com> ---
It seems to me that, as long as:

1) we rigorously stick to vector (SVP64, SUBVL) load, stores and operations on
vector registers,
2) stick to predication to access its sub-elements,
3) do not use non-SVP64 instructions on register previously used as vectors and
vice-versa,
4) do not change SUBVL on the same vector register

Then, the "endianess of the register file", and "VL indexing direction" should
become totally transparent (architecturally invisible). We can choose one mode
(say LE) and stick to it.

Just my two cents.

I do admit that, as I reread the thread, I'm still thoroughly confused.

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