[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

Cesar Strauss <cestrauss at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |cestrauss at gmail.com

--- Comment #51 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Alexandre Oliva from comment #38)
> uint8_t foo[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
> 
> ; r3 points to foo
>   ld r4, 0(r3)
>   ld r5, 8(r3)
>   setvli r0, 16
>   svp64 elwidth_src=8-bit mv r6.s, r4.v  

It seems to me that to manipulate vectors from memory, you must use vector
loads and stores as well, not mix scalar and vector as above. It should be
something like:

uint8_t foo[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
; r3 points to foo
  setvli r0, 16
  svp64 elwidth_src=8-bit ld r4.v, 0(r3)
  svp64 elwidth_src=8-bit ld r5.v, 8(r3)
  svp64 elwidth_src=8-bit mv r6.s, r4.v  

There is no byte-swapping in a vector of bytes, since a byte-swapped byte is
just itself. As for the byte order in a vector, note that even in bigendian
mode, a vector of bytes is stored sequentially (not byte-reversed every 8
bytes), see bottom of p25 on v3.0B spec.

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