[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #47 from Alexandre Oliva <oliva at libre-soc.org> ---
> the MSByte does NOT go into the MSByte but into the LSByte under the circumstances that you describe

sorry, but that's nonsense.  get some sleep and then think about what you just
said.  if it were true, then when you declared:

int64_t i = 1;

the moment i got loaded into a register, the 1, that is in the least
significant byte, would be moved to the most significant byte of the register,
and so on, with the most significant byte, that is a zero, landing in the
last-significant byte in the register.  i.e., the register would hold
72057594037927936 instead of 1.  that's not what you want from dword loads.

reversing bytes is something you do to move the MS bits in one representation
to the MS bits in another representation, and the LS bits in one representation
to the MS bits in the other representation.  You generally don't want to change
their significance, only their order.  You seem to have got them mixed up,
which may be caused by this dyslexia you mention, or even be the root cause
thereof.

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