[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #46 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here we go:

https://github.com/antonblanchard/microwatt/blob/39c826aa46a9dd80a12b572373c55d6156c4df07/execute1.vhdl#L1298

note the XNOR with MSR.LE.  MSR.LE=0 is processor BE mode.

table:

* LDST op is not brev variant LE clear i.e. BE - XNOR sets to 1
* LDST op is brev variant LE clear i.e. BE - XNOR sets to 0
* LDST op is not brev variant LE set - XNOR sets to 1
* LDST op is brev variant LE set - XNOR sets to 1

so yes i was correct.  the **NON BREV** variant when BE is set causes a
bytereversal inside LD/ST.

it was an XNOR operator not an XOR operator.

microwatt stores data in regfile in LE order and its ALUs are all processing in
LE order.

here's where the actual reversal is done, in LD/ST

https://github.com/antonblanchard/microwatt/blob/39c826aa46a9dd80a12b572373c55d6156c4df07/loadstore1.vhdl#L349

note that the opcode brev bit was XNORed with MSR.LE as input to that function.

confirmed, then:

it is definitely the case that MSByte of memory goes into LSByte of regfile
(and ALU) for a ld opcode when the processor is in BE mode.

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