[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #43 from Alexandre Oliva <oliva at libre-soc.org> ---
luke, *please* stick to what I'm writing and suggesting, not to your
imaginations and fears,

I have *not* objected to keeping registers in LE.  not at all.

I have *not* suggested adding bits to reverse byte order to any insn or prefix
or anything.

My suggestion was to iterate on sub-register vector elements in the
(corresponding-to-)memory endianness order: from LS to MS in LE, and from MS to
LS in BE.  that's all.

it's just about keeping the indexing in memory order, so that the vector does
operate as the same array, whether in memory or in registers, regardless of
whether you use the most specific or the most efficient memory operations
between them.

not doing that will set back the compiler development time for quite a while,
because we'll have to teach the compiler that the registers, when used in
vector mode, have endianness messed up in just the right way.  you know the
drill, it's a nightmare that we don't want to go through.

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