[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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             Status|CONFIRMED                   |DEFERRED

--- Comment #102 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #101)
> lkcl says he's fine with it as long as he doesn't have to do the work:
> https://libre-soc.org/irclog/%23libre-soc.2021-08-16.log.html#t2021-08-16T17:
> 45:38

no, i did not explicitly say that.  i have a very good idea of exactly how much
work is involved and i am not happy about it. i still have to be the one that
assesses its impact, and makes sure that the person doing the work
actually does a full, thorough and complete job. 

that still leaves me with a burden of responsibility for something that
i know will take a hell of a lot of work, and risks damaging SVP64 by making
it virtually impossible to understand.

also i said that the task has to include a full and complete comparative
analysis against using the existing solution (LDST-bytereverse (ldbrx)
when Vectorised, plus the Bytereverse mode of REMAP).

in addition to that we cannot keep on adding features (especially high
impact fundamental low-level ones like this which take up huge amounts
of time even just to assess).

this one remains firmly *off* the table until we have time and resources to
properly assess it and ensure it does not completely destroy 3+ years of
work.

bottom line is i am not on the least bit happy eith this, i do not like
it, i do not like that i cannot understand its impact enough precisely
because it is so complex and low level.

thus it shall remain deferred.

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