[Libre-soc-isa] [Bug 529] scheme for supporting 16/48-bit instructions on PowerPC LE with full backward compatibility

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=529

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> https://libre-soc.org/openpower/sv/major_opcode_allocation/
> 
> it's complicated but quite elegant, i like it.  i am trying to think through
> how mixed 16/32/48 would actually work.  it woukd be necessary i think to
> pop 16 bit instructions out of bytes 2+3 and leave 0+1 still at the front of
> the queue.

does this work? are there any cases where conceptually swapping bytes 0+1 with
2+3 at the memory level would not work? mixing 16/32/48 together?

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